The Memory Management Unit (MMU) translates an input address to an output address. This translation is based on address mapping and memory attribute information that is available in the internal registers and translation tables.
The MMU can cache the result of a translation table lookup in a Translation Lookaside Buffer (TLB). If TLB does not contain the required translation, the MMU requests translations from the memory by performing translation table walks.
AdoreSys’s MMU provides the following features:
- Lightweight SMMU with very small footprint
- Support for 40-bit virtual and physical addresses
- Support for 2MB, 8MB, and 64MB granule page sizes
- Support for up to 32 active translation contexts
- Scalable, configurable TLB that reduces the number of translation requests to memory
- MMU detects multiple translations requiring the same table in the TLB; if the TLB lookup results in a miss, the transaction waits until the table is available, reducing TLB lookup requests
- MMU detects multiple translations requiring the same table in memory, ensuring only one memory request is made
